The present application relates to semiconductor device manufacturing, and more particularly to a method of forming semiconductor devices containing functional gate structures which have different critical dimensions, i.e., gate lengths.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
Formation of functional gate structures having different critical dimensions is challenging, particularly in the context of forming such functional gate structures within a non-planar semiconductor device such as, for example, a finFET device. This challenge is further exacerbated by the continued progress towards smaller gate pitches, which are well below the lithography limits, making it harder to even pattern features that were feasible at larger pitches. In particular, providing devices with controlled differences in their gate length—a much desired feature—becomes extremely challenging. Non lithography based solutions like gate formation through multiple sidewall image transfer (SIT) are being considered for future technology nodes. There is a clear need for a simplified solution to this problem.